As a direct current source used in electronic devices such as a cellar phone, a DC input DC output DC—DC converter, for example, is widely employed. A synchronous rectifying DC—DC converter of a step-down type hitherto known as a type of this DC—DC converter (which will be simply referred to as a DC—DC converter as well). The driver is constituted from a CMOS inverter for switching a power supply voltage (DC input voltage) Vcc. The filter circuit smoothes the output of the driver and outputs a preset desired DC voltage (set DC voltage), and a control circuit controls the CMOS inverter.
In the DC—DC converter of the configuration described above, other components except for the filter circuit are integrated into the circuit and manufactured as the semiconductor integrated circuit for the DC—DC converter.
In a semiconductor integrated circuit for the DC—DC converter, there is a problem that a parasitic transistor is created, so that the DC—DC converter malfunctions due to a parasitic current.
An example of a semiconductor integrated circuit for a negative step-up circuit used in nonvolatile semiconductor storage devices such as a flash EEPROM (Electrically Erasable and Programmable Read Only Memory) is disclosed in Patent Document 1, for example. The semiconductor integrated circuit serves to prevent creation of a parasitic NPN transistor, and as shown in FIG. 9, the semiconductor integrated circuit is configured using an NMOS-type transistor of a triple-well structure. A Deep-N-well 202 is formed on a P-type silicon wafer 201, a P-well 203 is formed on this Deep-N-well 202, and a Deep-N-well terminal 209 having a floating potential is formed over this Deep-N-well 202. An NMOS-type transistor M201 is formed over the P-well 203, and nodes N202 and N203 are also formed over the P-well 203. To the nodes N202 and N203, capacitances C201 and C202 are connected, respectively.
According to the semiconductor integrated circuit of the configuration as described above, the P-well 203 and the Deep-N-well 202 are separated. Thus, each of their potentials can be set to a specific potential or the floating potential. Thus, it is described that even if a parasitic NPN transistor Q201 is created, potentials of a base and a collector thereof become floating ones, so that even if a base current Ib flows from the P-well 203 to the node N202 due to a step-up operation, a constant collector current Ie is not generated, and the parasitic NPN transistor Q201 can be thereby made to be ineffective.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2001-43690A